KWS SoC Hardware Requirements

SoC Design

Included Design Choices w/ Substantiation

Direct Memory Access (DMA) Controllers

DMA Controllers are needed to relieve CPU clock cycles, an example for this would be moving memory from the KWS sample FIFO to Internal memory, done by DMA, while CPU is put in low power or is processing another FIFO block.

Excluded Design Choices w/ Substantiation

Burst Transactions

Burst Transactions are not needed as AHB-Lite already does pipelining, in context of AHB-lite as mentioned in Burst transaction section in AHB-Lite Document:

Important

In 00 Basic 1 to 1 Interconnect bursts were introduced to allow back-to-back transactions, but this is already enabled by default by the pipelined nature of AHB-Lite, however bursts are supported because this can allow completers to prepare their internals for the data given in bursts possibly relieving some backpressure exerted on requester.

Bursts are not needed as:

I think this might be needed if completers dynamically allocate/reallocate memory internally, which should not be the case in our SoC.

  • ABP, which were I/O would connect to, does not support burst transactions.

Unneeded AHB-Lite Specs

HMASTLOCK is not needed as we would not have two managers fighting on a single address

HRESP is not needed as it is used mainly in hot, plug in system which is not the case for KWS SoC.

HPROT is also not needed in simpler SoCs, unneeded overhead.