02 AHB-Lite

This is more or less a summarization of Chapter 5, of Arm Fundamentals of SoC textbook, with note author's input

SoCs use on-chip buses, as all their components reside on the same die

AHB-Lite & APB Protocols

Originally developed by ARM but then became an open standard.

(Advanced High-Performance Bus Lite) AHB-Lite and (Advanced Peripheral Bus) APB completers are often used together in a system to allow high-performance subsystems to communicate through AHB-Lite, while low-power subsystems interface with their higher-power counterparts using the slower APB protocol to save power.

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Instead of requestors and completers, another terminology is used, Managers and Subordinates.

AHB-Lite

AHB-Lite provides an alternative solution to this bus utilization challenge by allowing managers to issue bus operations in a pipelined fashion. Thus, each operation consists of two phases:

  1. an address phase,
  2. a data phase.

To support even higher bandwidth, AHB-lite utilizes wide data buses.

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Some High-Level Observations
  • supports power-of-two bus sizes that range from 8 to 1024 bits.
  • There are extra signals on the Subordinate side, HREADY and HSEL, that is because multiple subordinates can be connected to the same manager and the AHB-Lite protocol designers decided to expose the extra signaling to handle this multiplicity on the subordinate side of the interconnect.

Implementation

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  • Notice that the HREADY signals from subordinate side are many while it is only one on the manager side, that is because if one completer is still carrying out a request on the bus it needs to finish before the next request is issued, this ensures requests are carried out in order in the pipelined nature of this implementation.
  • The address decoder is combinational, that means it is stateless yet the multiplexer must be stateful, the multiplexer must be stateful to avoid the infinite stalling problem outlined in 00 Basic 1 to 1 Interconnect
  • HSELx is outputted from address decoder, it selects the correct subordinate based on the address requested from the manager.
  • In contrast to the implementation in 00 Basic 1 to 1 Interconnect, we do not have a RD signal to subordinates, that is because we can use the off signal of HWRITE to signify read operations.
Due to the binary nature of the HWRITE signal, we cannot put bus in idle

Basic Operations

Write Operations

Assume these set of Write operations

Address Data
0x0 0xA
0x4 0xB
0x8 0xC
0xC 0xD
0x10 0xE

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Read Operation Waveform

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New Signals

HTRANS

HTRANS is a 2-bit signal sent from the manager to the subordinate to indicate the type of transfer being requested.

HTRANS Type Description
b00 IDLE notify the slave that this transfer does not need to be data transferred
b01 BUSY allows the master to insert idle cycles in the middle of a burst to achieve master-slave backpressure
b10 NONSEQ indicates a non-sequential transfer (single or first of a burst)
b11 SEQ indicates the current transfer is the subsequent transfer of a burst

Operation of HTRANS signal:

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HSIZE

Assume we are saving uint8_t or uint16_t in C, this operation would consume a lot of bus cycles if it is emulated as the data bus width would be fixed to 32 bit data buses, therefore we need a way for the requestor to signal to the completer the size of the data transaction so it can be done in one bus cycle.

HSIZE, a 3-bit signal that indicates the size of a single transfer in bytes.

HSIZE Size (bytes) Size (bits)
0b000 1 8
0b001 2 16
0b010 4 32
0b011 8 64
0b100 16 128
0b101 32 256
0b110 64 512
0b111 128 1024
Waveform

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HBURST

Why are Bursts Supported in AHB-Lite?

Important

In 00 Basic 1 to 1 Interconnect bursts were introduced to allow back-to-back transactions, but this is already enabled by default by the pipelined nature of AHB-Lite, however bursts are supported because this can allow completers to prepare their internals for the data given in bursts possibly relieving some backpressure exerted on requester.

Definitions
Each bus burst transfer is called a beat by AMBA.
Incrementing bursts
  • The address of the next beat is computed as , i.e. successive beats always have incrementing addresses.
Wrapping bursts
  • The address of the next beat is computed as , i.e. successive beats’ addresses wrap when they cross an address (or block-size) boundary defined by the product of the number of beats (defined by HBURST) and the data width (in bytes; defined by HSIZE).
Implementation
Warning

Note that the total amount of data transferred in a burst is defined by multiplying the number of beats by the amount of data in each beat (as conveyed through the HSIZE bus). This definition implies that HSIZE must remain constant throughout the burst and that the manager cannot change the data width between beats.

HBURST Name Description
0b000 SINGLE Single-beat burst
0b001 INCR Incrementing burst of undefined length
0b010 WRAP4 4-beat wrapping burst
0b011 INCR4 4-beat incrementing burst
0b100 WRAP8 8-beat wrapping burst
0b101 INCR8 8-beat incrementing burst
0b110 WRAP16 16-beat wrapping burst
0b111 INCR16 16-beat incrementing burst

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Backpressure

Subordinate to Manager

  • During a data phase, subordinates can deassert HREADY to insert wait states if they require more time to respond to a transfer, with the address phase of the next transfer only accepted when HREADY is high again.

Manager to Subordinate

Due to the pipelined nature of AHB-Lite, Address phase cannot be stalled

However, does it make sense for the manager to stall a single word transaction, it should support the word widths that it requests, otherwise it would use SEQ state.
Also, does it make sense for the manager to stall an IDLE state, it would just stall itself this way.
So AHB-Lite only supports stalling for burst transactions were the manager runs out of memory in internal buffers.

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Multi-Manager Systems

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The D and A components are the address decoder and the arbiter (a mux possibly?)

What would happen if M1 and M2 try to access the Same resource, say S1?

Locked Transfers

HMASTLOCK

Transfer Responses

HRESP

Protection Rings

HPROT